Currently, Intel Pentium microprocessor ALU unit has adapted Han Carlson Adder algorithm

-Tackdon Han Ph.D. Dissertation - University of Massachusetts at Amherst 1986


About Han Carlson Adder


( Fast Area-Efficient VLSI Adders by Tackdon Han and David A.Carlson [pdf] )

In this paper, we study area-time tradeoffs in VLSI for prefix computation using gragh representations of this problem. Since the problem is intimately related to binary additioin, the results we obtain lead to the design of area-time efficient VLSI adders. This is major goal of our work: to design very low latency addition circuitry that is also area efficient. To this end, we present a new graph representation for prefix computation that leadsto the design of a fast, area-efficient binary adder. The new graph is a combination of previously kmown graph representions ofr prefix computation, and is area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, we are able to desigh VLSI adders having area A = O( n log n) whose delay time is the lowest possible vlue, i.e. the fastest possible area-efficient VLSI adder.



Technology & Application Area


'Han-Carlson Adder' currently widely used in Intel Pentium Micro Processor and Sun Sparc Micro processor, and also heavily referenced and cited in many Journal papers, course lecture slide and Text book chapter. Reference for Han Carlson Adder


Intel Pentium 4 microprocessor

A 5Ghz 32b interger execution care in 130 nm Dual V Cmos by Intel Corp Hillsbore OR

"The 32 bit ALU is based on a single –ended, radix-2 Han Carlson adder core with 5 wide ultiplexor stages and write back bus"

Sub 500ps 64b ALUs in 0.18 micrM SOI/ Bulk CMOS Design and Scaling Trends

Intel Corp Intel Pentium 4 Microprocessor

“The 64 bit Han Carlson Adder Core designed in bulk CMOS technology forms our baseline design. Whils Han Carlson adder employs a logarithmic binary carry – carry merge scheme, similar to a Kogge Stone approach, the key difference between the two lines in the implementation of the carry merge tree

At equal performance, the Han Carlson adder consumes 43% less energy compared to the equivalent Kogge Stone implementation.

Sun Sparc Microprocessor

“When interconnected is considered, the Han Carlson adder and helper adders become most attractive. The Han Carlson Adder requires only the half the number of columns, while helper adders are slightly faster at driving the long wires“

Substrate Bias Optimized 0.18 2.5Ghz 32bit adder with post-manufacture Tunable adder

University of Wisconsin Madison

“The last one which was presented by Han and Carlson in 1987 has the lowest area-delay product. For this reason, we used a novel way to implement Han- Carlson’s work.”

Stanford University

Professor Horowitz – EE 371 Lecture 4 Slide – Han Carlson Adder

PP34 - Using this, we may expect a Han Carlson Adder to - Trade off logic layers for some increased wiring

University of Massachusetts

ECE 666 PP Han Carlson Adder – Small delay in exchange for high overall area and/or Power


References


Web Site

  • Adder Designs (Han-Carlson Adder) [Link]

Papers

  • Fine-Grained Redundancy in Adders (IEEE Compter Society) [Link]
  • Increasing Adder Efficiency by Exploiting Input Statistics [pdf]
  • Optimal Digital System Design in Deep Submicron Technology by Seongmoo Heo [pdf]

Books

  • Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage [ppt]
  • Stanford Universitt LectureNote (Adder) [pdf]

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